High performance, low cost, increased miniaturization and greater packaging density of integrated circuits have long been goals of the electronics industry. To meet the demand for smaller electronic products, there is a continuing drive to increase the performance of packaged microelectronic devices, while at the same time reducing the height and the surface area or “footprint” of such devices on printed circuit boards. Reducing the size of high performance devices, however, is difficult because the sophisticated integrated circuitry requires more bond-pads, which results in larger packages and more numerous external terminals, such as ball-grid arrays, and thus larger footprints. One technique for increasing the component density of integrated circuit devices within a given footprint is to stack one integrated circuit semiconductor die on top of another.
Although the use of stacked die integrated circuits has greatly increased the circuit density for a given footprint, coupling the dies to each other and to external terminals can be problematic. One approach is to use wire-bonds, in which miniature wires are attached to bonding pads on the die and to externally accessible terminals. However, wire bonding can be difficult, time consuming, and expensive because one die can overlie the bonding pads of another, thus making them inaccessible. It can also be necessary to route wires extending from one die to another around the peripheries of the dies. To alleviate these problems, “flip-chip” techniques have been developed in which the bonding pads of a first die are attached to a device, such as an interposer, through respective conductive elements to the bonding pads of a second die stacked on top of the first die. The conductive elements may comprise minute conductive bumps, balls, columns or pillars of various configurations. The first die is thus electrically and mechanically coupled to the second die. Unfortunately, flip-chip packaging requires that the first die be a mirror image of the second die. As a result, two separate semiconductor die must be laid out and manufactured, albeit the lay out task is relatively straightforward. Also, flip-chip packaging can unduly increase the cost, time, and complexity of packaging the die.
Another approach to interconnecting stacked die is the use of “through-wafer” interconnects. In this approach, conductive paths such as “vias” extend through a die to electrically couple bond-pads of a first die with corresponding bond-pads of a second die that is stacked on top of the first die. One advantage of this approach is that it allows for only a single die to be designed and manufactured. However, disadvantages of this approach include the time, expense and complexity of forming the conductive paths, and the surface area of the die that may be consumed by the conductive paths. Despite these disadvantages, through-wafer packing works very well, particularly for signals coupled to and/or from the same bonding pads on both die, such as, for memory devices, data and address signals. However, where separate signals must be coupled to and/or from corresponding bonding pads on each die, an extra bonding pad normally must be provided for both signals. Also, a routing circuit is fabricated on the die to couple the signals to and/or from the appropriate bonding pads. Furthermore, a second bonding pad and via are provided to couple a signal to control the routing circuit to one of the die. The result can be an undesirable proliferation in the number of external terminals, such as bond pads that are required, which can unduly increase the footprint of the integrated circuit.
It would therefore be desirable to minimize the number of external terminals needed for stacked die, through-wafer packaged integrated circuits.